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arinc inputs test inputs outputs v (a) - v (b) test a test b out a out b null 0 0 0 0 zero 0 0 0 1 one 0 0 1 0 don't care 0 1 0 1 don't care 1 0 1 0 don't care 1 1 0 0 general description the hi-8483 bus interface unit is a dual differential line re- ceiver in accordance with the requirements of the arinc 429 bus specification. the device translates incoming arinc 429 signals to normal cmos/ttl levels on each of its two independent receive channels. the hi-8483 is a functional alternative to the fairchild/raytheon rm3283 and dei3283. two ttl compatible self-test inputs for testing the arinc channels are available. they can be used to override the arinc input data and set the channel outputs to a known state. the self-test mode checks the entire circuit includ- ing the analog line receivers and digital logic. all the arinc inputs have built-in hysteresis to reject noise that may be present on the arinc bus. additional input noise filtering can also be accomplished with exter- nal capacitors. the hi-8483 is available in a variety of ceramic & plastic packages including small outline (soic) dip & leadless chip carrier (lcc). , features converts arinc 429 levels to digital data input hysteresis for superior noise rejection ttl and cmos outputs and test inputs military screening available 20-pin soic, dip & lcc packages are available ? ? ? ? ? ? replacement for rm3283 and dei3283 pin configurations (top views) truth table february 2012 hi-8483psi hi-8483pst hi-8483psm 20 - testb 19 - cap1a 18 - in1a 17 - cap1b 16 - in1b 15 - out1a 14 - gnd 13 - n/c 12 - out1b 11-+v s -v - 1 testa - 2 cap2b - 3 in2b - 4 out2b - 5 in2a - 6 cap2a - 7 out2a - 8 +v - 9 n/c-10 s l (ds8483 rev. a) 02/12 hi-8483 arinc 429 dual line receiver 20 - testb 19 - cap1a 18 - in1a 17 - cap1b 16 - in1b 15 - out1a 14 - gnd 13 - n/c 12 - out1b 11-+v s -v - 1 testa - 2 cap2b - 3 in2b - 4 out2b - 5 in2a - 6 cap2a - 7 out2a - 8 +v - 9 n/c-10 s l hi-8483cri hi-8483crt hi-8483crm 20 - pin plastic small outline package (soic) (see ordering information for additional pin configurations) 20 - pin ceramic dual in line package (cerdip) (see ordering information for additional pin configurations) holt integrated circuits www.holtic.com
hi-8483 block diagram +vs channel test circuitry output driver in2a in2b out2b gnd +vl out2a cap2a cap2b voltage reference threshold generator -vs out1b out1a cap1a cap1b in1a in1b output driver bit detection and level shifting hysteresis bit detection and level shifting hysteresis testa testb signal function description cap1a input filter capacitor input for terminal a of channel 1 cap1b input filter capacitor input for terminal b of channel 1 cap2a input filter capacitor input for terminal a of channel 2 cap2b input filter capacitor input for terminal b of channel 2 gnd power chip 0v supply in1a arinc input arinc 429 input terminal a of channel 1 in1b arinc input arinc 429 input terminal b of channel 1 in2a arinc input arinc 429 input terminal a of channel 2 in2b arinc input arinc 429 input terminal b of channel 2 out1a output ttl output terminal a of channel 1 out1b output ttl output terminal b of channel 1 out2a output ttl output terminal a of channel 2 out2b output ttl output terminal b of channel 2 testa input test input terminal a testb input test input terminal b +vl power +5 volts +/- 10% +vs power +15 volts +/- 10% -vs power -15 volts +/- 10% pin descriptions figure 1 - hi-8483 block diagram holt integrated circuits 2
hi-8483 holt integrated circuits 3 functional description the hi-8483 contains two independent arinc 429 receive channels, which take differently encoded arinc level data and convert it to serial ttl level data. the hi-8483 provides two complete analog line receivers and no external components are required. input level-shifting resistor networks allow arinc input voltage transients up to +/- 200v without damage to the hi- 8483. each channel is identical, featuring symmetrical delays for better high-speed performance. input common mode rejection is excellent and threshold voltage is stable, independent of supply voltage. data outputs are ttl and cmos compatible. two ttl compatible test inputs (testa and testb) used to simultaneously test both arinc channels are available. they can be used to override the arinc input data and set the channel outputs to a known state. the hi-8483 contains two discrete arinc 429 receiver channels. each channel contains three main sections: a resistor input network, a window comparator, and a logic output buffer stage. the first stage provides over-voltage protection and biases the signal using voltage dividers, providing excellent input common mode rejection. the testa and testb inputs are provided to set the outputs to a predetermined state for built-in channel test capability. if the test inputs are not used they should be grounded. the window comparator section detects data from the input resistor network. an arinc ?high? state generates a logic ?1? at outa and an arinc ?low? state generates a logic ?1? at outb. an arinc ?null? state at the inputs forces both outputs to logic ?0?. threshold and hysteresis voltages are generated by an on-chip voltage reference to maintain stable switching characteristics over temperature and supply voltage variations. the output stage generates a ttl compatible logic output capable of driving 3 ma of load. arinc levels the arinc 429 specification requires the following detection levels: one +6.5v to +13v null +2.5v to -2.5v zero -6.5v to -13v the hi-8483 guarantees recognition of these levels with a common mode voltage with respect to gnd less than 13v for the worst case condition. state differential voltage noise the input hysteresis is set to reject voltage level transi- tions in the undefined region between the maximum zero level and the minimum null level and the unde- fined region between the maximum null level and the minimum one level. therefore, once a valid input differential voltage threshold is detected, the outputs will remain at a valid logic state until a new valid input voltage is detected. the noise filter capacitors are optional and are added to provide extra noise immunity by limiting the bandwidth of the input signal before it reaches the window comparator stage. two capacitors are required for each channel and they must be of the same value. the suggested capacitor value for 100khz operation is 39 pf. for lower data rates, larger values of capacitance may be used to yield better noise performance. to get optimum performance, the following equation can be used to calculate capacitor value for a specific data rate: c= f where: c is the capacitor value in pf f is the input frequency 10 khz <= f <= 150 khz filter 0 filter 00 3.95 x 10 6
typical applications applications the standard connections for the hi-8483 are shown in figure 2. decoupling of the supply should be done near the ic to avoid propagation of noise spikes due to switching transients. the ground (gnd) connection should be sturdy and isolated from large switching currents to provide a quiet ground reference. the hi-8483 can be used with hi-8570 or hi-8585 line drivers to provide a complete analog arinc 429 interface solution. a simple application, which can be used in systems requiring a repeater type circuit for long transmissions or for test interfaces, is given in figure 3. more hi-8570 or hi-8585 drivers may be added to test multiple arinc channels, as shown. figure 2 - arinc receiver standard connections +5v +15v hi-8483 arinc channel 2 logic test inputs n/c n/c out2a out1a out1b a b a b 39 pf 39 pf 39 pf 39 pf in1a in1b cap1a cap1b in2a in2b cap2a cap2b testa testb arinc channel 1 channel 1 data out to logic channel 2 data out to logic -15v figure 3 - arinc repeater circuit arinc output channel 1 arinc output channel 2 arinc input channel data (a) data (b) data (a) data (b) out1a out1b in1a in1b aout bout aout bout hi-8570 or hi-8585 to additional channels a b a b hi-8570 or hi-8585 1/2 hi-8483 out2b hi-8483 holt integrated circuits 4
figure 5 testa testb +5v 0v +5v 0v t ptlh t pthl t ptlh t r t pthl t f 90% 10% 50% 50% outa (test) outb (test) 90% figure 4 arinc differential input +10v 0v -10v outa outb t plh t phl t plh t r t phl t f 10% 50% 50% timing diagrams hi-8483 holt integrated circuits 5
electrical characteristics 13.5v v 16.5v, +4.5v v +5.5v, operating temperature range (unless otherwise noted) << sl << hi-8483 limits parameter conditions unit symbol +vs (+15v) supply current i +/-vs = +/- 16.5v, vl = 5.0v test inputs = 0v 6.0 ma null - to - one transition v 5.70 6.30 v v(ina) - v(inb) test inputs = 0v, v(inb) = -2.50v ta = 25 c input resistance: differential (unpowered) r 3 50 k to gnd (unpowered) r 20 30 k input current: input sink i 200 a input source i -450 a input capacitance: differential c 10 pf (guaranteed but not tested) to gnd c 10 pf to v c 10 pf min typ max power supplies cc hh i g ih il i g dd h test inputs = 5v 6.0 ma -vs (-15v) supply current i +/-vs = +/- 16.5v, vl = 5.0v test inputs = 0v 12.0 ma test inputs = 5v 18.5 ma +vl (+5v) supply current i +/-vs = +/- 16.5v, vl = 5.0v test inputs = 0v 9.0 ma test inputs = 5v 17.5 ma +/-vs = +/- 15.0v, vl = 5.0v one - to - null transition v +/-vs = +/- 15.0v, vl = 5.0v 4.50 5.50 v v(ina) - v(inb) test inputs = 0v, v(inb) = -2.50v one - to - null transition hysteresis v vhh - vhl 0.8 1.2 v ta = 25c null - to - zero transition v +/-vs = +/- 15.0v, vl = 5.0v -6.30 -5.70 v v(ina) - v(inb) test inputs = 0v, v(inb) = +2.50v ta = 25c zero - to - null transition v +/-vs = +/- 15.0v, vl = 5.0v -5.50 -4.50 v v(ina) - v(inb) test inputs = 0v, v(inb) = +2.50v zero - to - null transition hysteresis v vll - vlh -1.2 -0.8 v ta = 25c input common-mode voltage range v -13 +13 v input resistor value: unpowered r ina to capa, inb to capb 8.5 10 11.5 k ina to inb, 0 ina to gnd, inb to gnd ina to inb arinc 429 inputs ee l hl hhys ll lh lhys cm in note: stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not imp lied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings voltage at arinc inputs: ...................................................-200v to +200v voltage at any other input:.............................................-0.3v to v + 0.3v output short circuit protected: .............................................not protected storage temperature range: .........................................-65c to +150c soldering temperature: (ceramic).................................60 sec. at +300c (plastic - leads)........................10 sec. at +280c (plastic - body) ................................+260c max. l supply voltage, +v : .....................................................................+20 vdc -v : .......................................................................-20 vdc +v : .......................................................................+7 vdc operating temperature range: (industrial) .........................-40c to +85c (hi-temp) ........................-55c to +125c (military) ..........................-55c to +125c internal power dissipation: ..............................................................900mw s s l +v to -v : ...........................................................+36 vdc ss (voltages referenced to gnd = 0v) holt integrated circuits 6
electrical characteristics (cont.) hi-8483 holt integrated circuits 7 limits parameter conditions unit symbol input voltage: input voltage hi v vs = +/-15v, vl=4.5v v input voltage lo v v input current: input sink i 300 a input source i -40 a min typ max logic inputs (testa, testb) ih il ih il 2.0 0.9 v = 5v, vs = +/-15v, vl=5v v = 0.8v, vs = +/-15v, vl=5v output voltage: input voltage hi v vs = +/-15v, vl=5v i = -100 a (ta = 25c) 4.0 v i = -2.8 ma 3.5 v input voltage lo v vs = +/-15v, vl=5v i = 100 a (ta = 25c) 0.1 v i = 2.0 ma 0.8 v output rise time t cl - 60 pf 10 70 ns output fall time t cl - 60 pf 10 70 ns propagation delay ina/b to outa/b rising edge t capa, capb, cl = 60 pf 700 ns ina/b to outa/b falling edge t capa, capb, cl = 60 pf 700 ns matching of tplh and tphl t 500 ns testa/b to outa/b rising edge t cl = 60 pf, vin = 0.8v/2.0v 700 ns testa/b to outa/b falling edge t cl = 60 pf, vin = 0.8v/2.0v 700 ns ih il oh oh ol ol r f logic outputs (outa, outb) timing parameters oh ol plh phl dtp ptlh pthl | tplh - tphl | part number f blank lead finish tin / lead (sn / pb) solder 100% matte tin (pb-free, rohs compliant) hi - 8483 (plastic wide body soic) ps x x temperature range flow burn in -40c to +85c no i part number i -55c to +125c no t t -55c to +125c yes m m ordering information & thermal characteristics 13.5v v 16.5v, +4.5v v +5.5v, operating temperature range (unless otherwise noted) << sl << part number ja ps 20 pin plastic soic wide body package (20hw) jc thermal res . 17c/w 90c/w package description
ordering information & thermal characteristics (cont.) hi - 8483 (20-pin cerdip) cr x temperature range flow burn in -40c to +85c no i -55c to +125c -55c to +125c no yes t m part number t m i lead finish tin / lead (sn / pb) solder part number ja cl 20 pin ceramic leadless chip carrier (20s) jc thermal res . 25c/w 85c/w package description hi-8483 tin / lead (sn / pb) solder tin / lead (sn / pb) solder hi - 8483 (20-pin ceramic lcc) cl x 20 pin cerdip (20d) part number ja jc thermal res. cr 28c/w 90c/w package description temperature range flow burn in -40c to +85c no i -55c to +125c -55c to +125c no yes t m part number t m i lead finish tin / lead (sn / pb) solder gold gold additional hi-8483 pin configuration 18 - in1a 17 - cap1b 16 - in1b 15 - out1a 14 - gnd 3 - cap2b 2 - testa 1--v 20 - testb 19 - cap1a s in2b - 4 out2b - 5 in2a - 6 cap2a - 7 out2a - 8 +v - 9 n/c - 10 +v - 11 out1b - 12 n/c - 13 l s HI-8483CLI hi-8483clt hi-8483clm 20 - pin ceramic leadless chip carrier (lcc) (see first page of data sheet for additional pin configurations) holt integrated circuits 8
revision history dwg. no. rev. date description of change ds8483 new 03/22/10 initial release a 02/29/12 correct typo in part numbers on ordering information, page 8. change soldering temperature (plastic - body) in absolute maximum ratings from 220c to 260c. hi-8483 holt integrated circuits 9
hi-8483 package dimensions 20-pin plastic small outline (soic) - wb (wide body) inches (millimeters) package type: 20hw bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) .5035 .0075 (12.789 .191) .4065 .0125 (10.325 .318) .295 .002 (7.493 .051) 0 to 8 .090 .010 (2.286 .254) .0075 .0035 (.191 .089) .018 (.457) typ see detail a detail a .033 .017 (.838 .432) .0105 .0015 (.2667 .0381) .050 (1.27) bsc 20-pin cerdip inches (millimeters) package type: 20d bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) 1.060 max (26.924 max) .005 min (.127 min) .070 max (1.778 max) .288 .005 (7.315 .127) .060 typ (1.524 typ) .015 min (.381 min) .200 max (5.080 max) .125 min (3.175 min) .018 .003 (.457 .760) 0 to 15 .010 .002 (.254 .051) .310 .010 (7.874 .254) .170 max (4.318 max) .100 bsc (2.54) holt integrated circuits 10
hi-8483 package dimensions 20-pin ceramic leadless chip carrier inches (millimeters) package type: 20s bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) pin 1 .020 (.508) .040 x 45 (1.016 x 45) .175 .004 (4.445 .101) .009r .006 (.229r .152) .050 .005 (1.270 .127) .350 .008 (8.890 .203) sq. .080 .020 (2.032 .508) .050 (1.270) .075 .004 (1.905 .101) .025 .003 (.635 .076) pin 1 bsc index 3 plcs holt integrated circuits 11

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